The present application claims priority to Japanese Application No. P10-282992 filed Oct. 5, 1998 which application is incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
This invention relates to a plasma addressed liquid crystal display device comprised of an electro-optical display cell, having a layer of an electro-optical material, and a plasma cell, operating as a scanning switch, are layered together with a dielectric sheet in-between.
2. Description of the Related Art
Heretofore, a plasma addressed liquid crystal display device has been proposed, which is comprised of an electro-optical display cell and a plasma cell, layered together with a dielectric sheet in-between.
A plasma addressed liquid crystal display device 100 includes a flat panel structure comprised of an electro-optical display cell 101, a plasma cell 102 and an interposed dielectric sheet 103, layered together, as shown in FIGS. 1 and 2. The dielectric sheet 103 is constructed by, for example, a thin glass sheet. For driving the display cell 101, the dielectric sheet 103 needs to be as thin as possible and is formed to a sheet thickness of, for example, 50 xcexcm.
The display cell 101 is constructed using an upper glass substrate (front side substrate) 104. On an inner major surface of the front side substrate 104, there are plural data electrodes 105 of a transparent electrically conductive material, extending in the horizontal direction and which is layered side-by-side in the row direction (vertical direction). The front side substrate 104 is bonded to the dielectric sheet 103 with a pre-set gap by a spacer. In the gap between the front side substrate 104 and the dielectric sheet 103 is formed a liquid crystal layer 107 by charging a liquid crystal as an electro-optical material. The gap between the front side substrate 104 and the dielectric sheet 103 is of the order of, for example, 4 to 10 xcexcm, and is kept uniformly over the entire display surface.
The plasma cell 102 is constructed using a lower transparent glass substrate (rear side substrate) 108. On the inner major surface of the front side substrate 104, plural anode electrodes 109A and plural anode electrodes 109K, constituting a plasma electrode, are alternately formed side-by-side in the column direction as a pre-set gap is maintained therebetween. At the mid portions of the upper surfaces of the anode electrodes 109A and anode electrodes 109K are formed barrier ribs 110 of a pre-set with for extending along the electrodes. The upper ends of the barrier ribs 110 are abutted against the lower sides of the dielectric sheet 103 to maintain a constant size of the gap between the rear side substrate 108 and the dielectric sheet 103.
On the rim portions of the rear side substrate 108 is arranged a frit seal material 111 of, for example, a low-melting glass, for extending along the rim portions, for air-tightly bonding the rear side substrate 108 and the dielectric sheet 103. In a gap between the rear side substrate 108 and the dielectric sheet 103 is sealed an ionizable gas.
In the gap between the rear side substrate 108 and the dielectric sheet 103 are arranged plural discharge channels 112 for extending side-by-side along the row direction. The discharge channels 112 are separated from one another by respective partitions 110.
That is, the discharge channels 112 are formed at right angles to the data electrodes 105, which operate as row driving units. The anode electrodes 109A are connected in common and fed with the anode voltage, as will be explained subsequently, so that paired discharge channels 112, disposed on either sides of the cathode electrodes 109K, prove column driving units. At each intersection of the anode and cathode electrodes is defined a pixel 113, as shown in FIG. 3.
If, in the above structure, a pre-set voltage is applied across the anode electrode 109A and the cathode electrode 109K corresponding to the pre-set paired discharge channels 112, the gas in the paired discharge channels 112 is selectively ionized to generate plasma discharge, the inside of which is maintained at an anode potential. If, in this state, the data voltage is sequentially applied to the data electrodes 105, the data voltage is written via dielectric sheet 103 to the liquid crystal layer 107 of the plural pixels 113 arrayed in the row direction in register with the paired discharge channels 112. On completion of the plasma discharge, the discharge channels 112 are at a floating potential, such that the data voltage written in the liquid crystal layer 107 of each pixel 113 is held by the operation of the dielectric sheet 103 until the next writing period, such as after one frame. In this case, the discharge channel 112 operates as a sampling switch, with the liquid crystal layer 107 of each pixel 113 and/or the dielectric sheet 103 operating as sampling capacitors.
Since the liquid crystal operates by the data voltage written in the liquid crystal layer 107 of each pixel 113, display is on the pixel basis. By generating the plasma discharge for sequentially scanning in the column direction the paired discharge channels 112 for writing the data voltage in the liquid crystal layer 107 of plural pixels 113 arrayed in the row direction, it is possible to display a two-dimensional image.
FIG. 4 shows a circuit structure of the plasma addressed liquid crystal display device 100. In FIG. 4, the reference numeral 121 is a liquid crystal driver to which video data is supplied. To this liquid crystal driver 121 is supplied video data. From the liquid crystal driver 121, data voltages DS1 to DSm of plural pixels, constituting a scanning line, are outputted simultaneously every horizontal period. Data voltages DS1 to DSm of plural pixels constituting the respective lines are outputted from the liquid crystal driver 121 every horizontal period. These plural voltages DS1 to DSm are routed via respective buffers 1221 to 122m to the plural data electrodes 1051 to 105m.
The operation of the liquid crystal driver 121 is controlled by a control circuit 123, which is fed with horizontal synchronization signals HD and the vertical synchronization signals VD corresponding to video data. The operation of a anode driver 124 and a cathode driver 125, as later explained, is also controlled by this control circuit 123.
To the plural anode electrodes 109A1 to 109An, connected in common by the anode driver 124, an anode voltage VA, as a reference voltage, is supplied. To the plural cathode electrodes 109K1 to l09Knxe2x88x921, cathode voltages VK1 to VKnxe2x88x921, having pre-set potential differences from the anode potential, are supplied by the cathode driver 125 every horizontal period. In this manner, plasma discharge is sequentially produced in the paired discharge channels 112 associated with the cathode electrodes VK1 to VKnxe2x88x921, so that the paired discharge channels 112 for writing the data voltages DS1 to DSm in the liquid crystal layer 107 of the plural pixels 113 arrayed in the row direction are sequentially scanned in the column direction.
The cathode voltage applied to te cathode electrode 109K and the data voltage DS applied to the data electrode 105 are explained. FIGS. 5A to 5D show the cathode voltages VKa to VKa+3 applied to the cathode electrodes 109Ka to 109Ka+3, respectively. FIG. 5E shows the data voltage DS applied to the pre-set data electrode 105. To the cathode electrodes 109Ka to 109Ka+3, cathode voltages VKa to VKa+3, lying at pre-set potential differences from the anode potential, are applied during each one horizontal period (1H) on the frame basis. This sequentially scans the discharge channels 112, generating the plasma discharge, in the column direction (in the horizontal direction). The data voltage DS is inverted in polarity with respect to the anode potential every horizontal period and every frame tin order to AC-drive the liquid crystal layer 107. The purpose of the AC-driving of the liquid crystal layer 107 is to prevent deterioration of the liquid crystal.
In the above-described plasma addressed liquid crystal display device 100, the data voltage DS is written by ions and/or electrons, generated by the plasma discharge (DC discharge), charging up the lower surface of the dielectric sheet 103 (surface towards the plasma cell 102 of the dielectric sheet 103). In the case of the plasma addressed liquid crystal display device, in which writing is by the DC discharge, it is a frequent occurrence that uniform discharge current density cannot be obtained on the entire discharge channel, under the effect of surface states of the cathode electrode 109K, fluctuations in structure or the data electrode units, such that stable display cannot be obtained on the entire viewing screen.
For example, in DC discharge, the discharging portion is more liable to discharging by positive feedback, thus producing localized discharge. If the data voltage DS is of the same polarity as the cathode voltage, as the discharging driving voltage, and moreover is of the same polarity as the anode potential (reference potential), the electrical field within the discharging channels becomes weak to suppress discharge.
It is therefore an object of the present invention to provide a plasma addressed liquid crystal display device whereby stable display can be realized on the entire area of the viewing screen.
In one aspect, the present invention provides a plasma addressed liquid crystal display device having a plurality of plasma channels each having discharge electrodes for plasma discharge, the plasma channels being partitioned by parallel partitions associated with reference electrodes, the discharge electrodes being covered by a plurality of dielectric members, wherein the discharge electrodes are formed by a pair of transparent electrodes having pre-set electrode widths and electrode intervals and a bus electrode formed of a material lower in the electrical resistance than the material of the transparent electrode and which is arranged for extending along the transparent electrode in association with each transparent electrode.
Preferably, the discharge electrodes are arranged so that the bus electrode is positioned towards the partition and the transparent electrode is positioned at a mid portion of the plasma channel. The material of the transparent electrode is ITO. The bus electrode is of a chromium-copper-chromium layered structure. The resistance value of the bus electrode preferably is not larger than 200 xcexa9/m per line.
If the interval between transparent electrodes is d, the electrode width of the transparent electrode is L and the height of the partition is h, the relation (d+L) less than h preferably holds. Also, if the thickness of the dielectric layer is t1, the relation (d+L) greater than t1 preferably holds.
The reference electrode can be arranged at a mid portion of each partition. The resistance value of the reference electrode preferably is not higher than 200 xcexa9/m per line. The wiring interconnecting the reference electrodes of the respective channels is formed at a dead zone of a dielectric pattern. Preferably, a contact hole interconnecting the reference electrode and the substrate is also formed at a dead zone of the dielectric pattern.
If the dielectric constant of a dielectric layer is ∈1, the thickness of the dielectric layer is t1, the dielectric constant of the dielectric sheet separating the transparent electrode and the liquid crystal layer from each other is ∈2 and the thickness of the dielectric sheet is t2, the relation (∈1/t1) less than 5(∈2/t2) preferably holds.
The pattern of the dielectric layer is partially overlapped with a frit seal pattern. The sealed gas preferably contains not less than 3% of a xenon gas. The sealed gas preferably has a pressure equal to not less than 50 Torr to not higher than 400 Torr at ambient temperature. Preferably, a protective layer is provided on at least a dielectric layer. The protective layer is formed of MgO and has a thickness not less than 0.1 xcexcm and not larger than 5 xcexcm.
With the liquid crystal display device according to the present invention, the plasma addressed liquid crystal display device has a plurality of plasma channels each having discharge electrodes for plasma discharge, the plasma channels being partitioned by parallel partitions associated with reference electrodes, the discharge electrodes being covered by a plurality of dielectric members. The discharge electrodes are formed by a pair of transparent electrodes having pre-set electrode widths and electrode intervals and a bus electrode of a material lower in the electrical resistance than the material of the transparent electrode arranged in association with each transparent electrode. With the present plasma addressed liquid crystal display device, stable display can be obtained in the entire area of the viewing screen.